1. Field of the Invention
The invention relates to a method of fabricating non-volatile semiconductor memory devices, and more particularly to a memory device employing local sources having improved coupling ratio.
2. Description of the Prior Art
The trend of recent semiconductor device developing is that high density non-volatile memory has been expected to replace some part of the huge external storage device market of computers, because of its easy to access and low power dissipation.
Please refer now to FIG. 1, there is shown a cross sectional view of the conventional stack non-volatile memory array cell. A tunnel oxide 2 and a first polysilicon 3A layers are grown on a semiconductor substrate 1. The tunnel oxide layer and the first polysilicon layers are patterned by the conventional lithography and plasma-etching techniques to form the floating gates. A first dielectric 4 and a second polysilicon 5A layers are then deposited overlaying the floating gates. The first dielectric layer is typically made of oxide/nitride/oxide (ONO) sandwich structure. Thereafter, the control gates are patterned.
Next, source 6 and drain 7 regions are formed by ion implanting dopants into the semiconductor substrate which is not covered by the gates. A second dielectric layer 8 (usually made of doped oxide) is deposited on the entire substrate surface. Finally, contact windows 9 are opened by lithography and plasma-etching techniques again. The basic structure of a non-volatile memory cell is completed. Referring now to FIG. 2, there is shown the cell layout corresponding to FIG. 1. The areas marked 10 are the isolation regions.
According to the description above, there must be a contact window for every two cells that limits the packing density of the memory array. Besides, the silicon substrate which is not covered by the first polysilicon (S area of FIG. 2) has great possibilities to be undercut during the self-aligned etching process, which increases the resistance of the source lines. Furthermore, the distance between two adjacent metal lines is too close when cell size continuously shirking that creates cross talk problem. All these drawbacks degrade the performance of the non-volatile memory arrays. Therefore, the present invention provides a new design approach which reduces the cell area compared with the conventional cell without suffering the above problems.